KM48S8030C Datasheet (Samsung semiconductor) - 2M x 8Bit x 4 Banks Synchronous DRAM

KM48S8030C, 2M x 8Bit x 4 Banks Synchronous DRAM

The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock c

KM48S8030C Features

* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at