* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at
KM48S8030C Datasheet (82.55 KB)
KM48S8030C
Samsung semiconductor
82.55 KB
2m x 8bit x 4 banks synchronous dram.
KM48S8030C
Revision History
Revision 0.0 (Oct., 1998)
* PC133 first published.
Preliminary PC133 CMOS SDRAM
REV. 0 Oct. '98
KM48S8030C
2M x.
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