KM48S8030D Datasheet (Samsung semiconductor) - 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

KM48S8030D, 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

The KM48S8030D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock c

KM48S8030D CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 May 1999 Samsung Electronics reserves the right to change products or specification without notice.

Rev.

0.0 May 1999 KM48S8030D Revision History Revision 0.0 (May 15, 1999) CMOS SDRAM Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.

Skip ICC4 value of CL=2 in DC characteristics in datasheet.

Define a new parameter of tDAL( 2CLK +20ns), Last data in to A

KM48S8030D Features

* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled a