K7A403600M Datasheet (Samsung) - 128K x 36 Synchronous SRAM

K7A403600M, 128K x 36 Synchronous SRAM

The K7A403600M is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

It is organized as 128K words of 36bits and integrates address and control registers, a 2-bit burst address counter and added some new func

K7A403600M Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev.

No.

0.0 0.1 0.2 0.3 History Initial draft Change 7.5 bin to 7.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85 Draft Date May .

15.

1997 January .

13 .

1998 February.

02.

1998 Remark Preliminary Preliminary Preliminary Preliminary Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change February.

12.

1998 Input/output leackage currant for ±1µA to ±2µA Modify Re

K7A403600M Features

* Synchronous Operation.

* 2 Stage Pipelined operation with 4 Burst.

* On-Chip Address Counter.

* Self-Timed Write Cycle.

* On-Chip Address and Control Registers.

* VDD= 3.3V+0.3V/-0.165V Power Supply.

* VDDQ Supply Voltage 3.3V+0.3V/-0.165V fo