K7A403600M Datasheet - Samsung

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K7A403600M 128K x 36 Synchronous SRAM

K7A403600M Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev.No.0.0 0.1 0.2 0.3 History In.
The K7A403600M is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC bas.

K7A403600M_Samsung.pdf

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Datasheet Details

Part number:

K7A403600M

Manufacturer:

Samsung

File Size:

307.80 KB

Description:

128K x 36 Synchronous SRAM

Features

* Synchronous Operation.
* 2 Stage Pipelined operation with 4 Burst.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* VDD= 3.3V+0.3V/-0.165V Power Supply.
* VDDQ Supply Voltage 3.3V+0.3V/-0.165V fo

Applications

* GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address

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