* put signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable IOL = 0 mA Page burst 2Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V 3 2 CAS Latency PC66 SDRAM
KMM366S403CTL Datasheet (162.23 KB)
KMM366S403CTL
Samsung
162.23 KB
Pc66 sdram module.
KMM366S403CTL Revision History Revision .3 (Mar. 1998) PC66 SDRAM MODULE Some Parameter values & Characteristics of comp. level are changed.
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