* q q q q q Super-high density (adopting 0.45µm silicon gate CMOS with 2- and 3-metal layers) High-speed operation (operation delay of internal gate = 0.160ns at 3.3V, 2-input power NAND standard) Internal gate = 3.3 and 3.0V (2.0V single), I/O buffer = 5.0, 3.3 and 3.0V (2.0V single) (built-in level
SLA4028
Seiko Epson Corp
34.13 KB
High density gate array.
PF842-02
SLA40000 Series
High Density Gate Array
q Super-high-density/speed gate array q Operates on 3.3 and 3.0V power source (level shifter is pre-.
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