HYB5117805BJ-50 Datasheet - Siemens

HYB5117805BJ-50 2M x 8 - Bit Dynamic RAM 2k Refresh

DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) VCC VSS N.C. Semiconductor Group 2 HYB5117805BSJ-50/-60/-70 2M x 8-EDO DRAM P-SOJ-28-3 400 mil VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 VCC O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19.

2M x 8 - Bit Dynamic RAM 2k Refresh (Hyper Page Mode- EDO) Advanced Information HYB5117805BSJ -50/-60/-70 2 097 152 words by 8-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns Single + 5 V (± 10 %) supply Low power dissipat.

HYB5117805BJ-50 Features

* include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5117805BJ-50 HYB 5117805BJ-60 HYB 5117805BJ-70 Pin Names A0-A10 A0-A9 RAS OE I/O1-I/O8 CAS WE Row Address Inputs Column Address Inputs Row Ad

HYB5117805BJ-50 Datasheet (258.42 KB)