HYS72V2100GU-10 Datasheet (Siemens) - 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module

HYS72V2100GU-10, 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module

PC66 2M x 64 SDRAM module PC66 2M x 72 SDRAM module PC66 2M x 64 SDRAM COB module PC66 2M x 72 SDRAM COB module Pin Names A0-A10 A11 (BS) DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 Address Inputs( RA0 ~ RA10 / CA0 ~ CA8) Bank Select Data Input/Output Check Bits (x72 organisation only) Row Address Strobe C

3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module 168 pin unbuffered DIMM Modules HYS64V2100G(C)U-10 HYS72V2100G(C)U-10 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module for PC main memory applications 1 bank 2M x 64, 2M x 72 organisation Optimized for byte-write non-parity or ECC applications Fully PC66 layout compatible JEDEC standard Synchronous DRAMs (SDRAM) Performance: -10 fCK tAC Max.

Clock frequency Max.

access time from clock 66 MHz @ CL=2 100 MH

HYS72V2100GU-10 Features

* d after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured