The SiS5501(PCMC) bridges between the host bus and the PCI local bus.
The SiS5501 (PCMC) monitors each cycle initiated by the CPU, and forwards it to the PCI bus if the CPU cycle does not target the local memory.
For the CPU or the PCI bus to the local memory cycles, the built-in Cache and DRAM Cont
www.DataSheet4U.com Pentium/P54C PCI/ISA Chipset 1 5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Memory Controller (PCMC) PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the SiS5501, 5502, and 5503 provides fully integrated support for the Pentium/P54C PCI/ISA system.
The chipset is developed by using a very high level of function integration and system partitioning.
With the SiS5501, SiS5502, and SiS5503 chipset, only 12 TTLs (include 3 DRAM address buffer) a
SIS5501 Features
* Supports the 51060, 56766, 73590, 815100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium Compatible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through an
SIS5502_SiliconIntegratedSystem.pdf
Datasheet Details
SIS5501, SIS5502
Silicon Integrated System
632.88 KB
Pci/isa cache memory controller.
This datasheet PDF includes multiple part numbers: SIS5501, SIS5502.
Please refer to the document for exact specifications by model.
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