SGN04G72G2BQ2SA - 204 Pin ECC SO-UDIMM

Swissbit

Datasheet Details

204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double Data Rate synchronous DRAM Module Module organization: dual rank 512M x 72 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V 1.5V I/O ( SSTL_15 compatible) Fly-by-bus with termination for C/A & CLK bus 2 On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM This module is fully pin and functional compatible to the JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design spec. and JEDEC- Standard.

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Published: Jun 18, 2014 |