* (1) AEC-Q101 qualified (2) Low drain-source on-resistance: RDS(ON) = 17 mΩ (typ.) (VGS = -10 V) (3) Low leakage current: IDSS = -10 µA (max) (VDS = -40 V) (4) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Internal Circuit TJ20S04M3L DPAK+ 1: Gate 2: Drain (heat
TJ20S04M3L Datasheet (254.37 KB)
TJ20S04M3L
254.37 KB
Silicon p-channel mosfet.
MOSFETs Silicon P-Channel MOS (U-MOS) TJ20S04M3L 1. Applications Automotive Motor Drivers DC-DC Converters Sw.
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