Description
(4-BANK x 16,777,216-WORD x 4-BIT) (4-BANK x 8,388,6084-WORD x 8-BIT) (4-BANK x 4,194,304-WORD x 16-BIT)
A2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and A2V56S30BTP is organized as 4-bank x 8,388,608-word x 8-bit and A2V56S40BTP is organized as 4-bank x 4,194, 304-word x 16-bit.All inputs and outputs are referenced to the rising edge of CLK.A2V56S20BTP,A2V56S30BTP and A2V56S40BTP achieve very high speed clock rates up to 166MHz, and are
Features
- ITEM
tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min. ) CL=2 CL=3
-6
6 42 CL=2 CL=3 V56S20 15 5 60 100 110 130 3
A2V56S20/30/40BTP -7E -7 -75 -8
7 7 45 20 5.4 5.4 63 100 110 130 3 7 45 20 5.4 63 100 110 130 3 10 7.5 45 20 6 5.4 67.5 100 110 130 3 10 8 48 20 6 6 70 95 100 120 3
Unit ns ns ns ns ns ns ns mA mA mA mA
Active to Precharge Command Period (Min. ) (Min. ) Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) (Max. ) (Min. ) (Max. ) V56S30 V.