Datasheet4U Logo Datasheet4U.com

UR5595 - DDR TERMINATION REGULATOR

Description

The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM.

Features

  • S.
  • Power regulating with driving and sinking capability.
  • Low output voltage offset.
  • No external resistors required.
  • Low external component count.
  • Linear topology.
  • Low cost and easy to use.
  • Thermal shutdown protection.

📥 Download Datasheet

Datasheet preview – UR5595

📁 Similar Datasheet

  • UR5HC418 - AT / PS/2 - Compatible Keyboard Encoder (Semtech Corporation)
  • UR5HC418-FB - AT / PS/2 - Compatible Keyboard Encoder (Semtech Corporation)
  • UR5HC418-FN - AT / PS/2 - Compatible Keyboard Encoder (Semtech Corporation)
  • UR5HC418-P - AT / PS/2 - Compatible Keyboard Encoder (Semtech Corporation)
  • UR5HC703-600-FG - USAR SerialCoderTM Low-Power Keyboard Encoder interfaces RS-232 (Semtech Corporation)
  • UR5HC703-600-FQ - USAR SerialCoderTM Low-Power Keyboard Encoder interfaces RS-232 (Semtech Corporation)
  • UR5HCFJ8 - Low-Power Keyboard Encoder for Portable Systems (Semtech Corporation)
  • UR5HCFJ8-FB - Low-Power Keyboard Encoder for Portable Systems (Semtech Corporation)
  • UR5HCFJ8-FN - Low-Power Keyboard Encoder for Portable Systems (Semtech Corporation)
  • UR5HCFJ8-P - Low-Power Keyboard Encoder for Portable Systems (Semtech Corporation)
Other Datasheets by UTC
  • UR5596 - DDR TERMINATION REGULATOR
  • UR5512 - 2A DDR BUS TERMINATION REGULATOR
  • UR5515 - 1.5A/3A BUS TERMINATION REGULATOR
  • UR5516 - 3A BUS TERMINATION REGULATOR
  • UR5516A - 3A BUS TERMINATION REGULATOR
  • UR5516B - 3A BUS TERMINATION REGULATOR
  • UR5517 - 3A DDR BUS TERMINATION REGULATOR
  • UR5025 - 2 CHANNEL LOW-DROPOUT VOLTAGE REGULATOR

Full PDF Text Transcription

Click to expand full text
UNISONIC TECHNOLOGIES CO., LTD UR5595 DDR TERMINATION REGULATOR CMOS IC  DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the UR5595 can provide superior load regulation. The UR5595 provides a VREF output as the reference for the application of the chipset and DIMMs. The output, VTT, is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2.
Published: |