UR5595 Datasheet - UTC

UR5595 DDR TERMINATION REGULATOR

The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A.

UR5595 Features

* Power regulating with driving and sinking capability

* Low output voltage offset

* No external resistors required

* Low external component count

* Linear topology

* Low cost and easy to use

* Thermal shutdown protection

* ORDERING INFORMATION Ordering Number UR55

UR5595 Datasheet (317.37 KB)

UR5595 Datasheet Preview — Preview of UR5595 PDF

Datasheet Details

Part number:

UR5595

Manufacturer:

UTC

File Size:

317.37 KB

Description:

Ddr termination regulator.

📁 Related Datasheet

UR5596 DDR TERMINATION REGULATOR (UTC)

UR5512 2A DDR BUS TERMINATION REGULATOR (UTC)

UR5515 1.5A/3A BUS TERMINATION REGULATOR (UTC)

UR5516 3A BUS TERMINATION REGULATOR (UTC)

UR5516A 3A BUS TERMINATION REGULATOR (UTC)

UR5516B 3A BUS TERMINATION REGULATOR (UTC)

UR5517 3A DDR BUS TERMINATION REGULATOR (UTC)

UR5025 2 CHANNEL LOW-DROPOUT VOLTAGE REGULATOR (UTC)

TAGS

UR5595 DDR TERMINATION REGULATOR UTC

UR5595 Distributor