Description
5
1. Clock Logic 5 2. CPU Interface 6 3. Co-processor Interface 6 4. Local Bus Interface 7 5. Advanced Cache Controller 7
5.1. Write-back and write-through Cache Schemes 7 5.2. Cache Organization 8 5.3. Cache Operation 9 5.4. Cacheable Region 10 5.5. Cache Parameters11
6. Page Mode DRAM Controller 12 7. Shadow RAM and ROM Decoding 14 8. ISA Bus Controller 15 9. Local Bus IDE Controller 16
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VIA Technologies, Inc.Table of Contents
10.Power Management Unit 17
10.1. Primary/Secondar
Features
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1. Fully IBM PC/AT Compatible 1 2. Flexible CPU and Local Bus Interface 1 3. Advanced Cache Controller 1 4. Fast Page Mode DRAM Controller 1 5. Synchronous ISA Bus Controller 2 6. Integrated Power Management Unit 2 7. Integrated Local Bus IDE Controller 2 8. High Integration and Complete Functionality 2 9. 0.8um high speed and low power CMOS process 2 10.208-pin PQFP package 2
Overview 3
Functional.