Datasheet4U Logo Datasheet4U.com

XC2S100 Datasheet - Xilinx

XC2S100 Spartan-II FPGA

DS001-2 (v2.9) March 12, 2021 * Architectural Description - Spartan-II Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan * Development System * Configuration - Configuration Timing * Design Consid.

XC2S100 Datasheet (0.97 MB)

Preview of XC2S100 PDF
XC2S100 Datasheet Preview Page 2 XC2S100 Datasheet Preview Page 3

Datasheet Details

Part number:

XC2S100

Manufacturer:

Xilinx

File Size:

0.97 MB

Description:

Spartan-ii fpga.

📁 Related Datasheet

XC2S100E Spartan-IIE FPGA (Xilinx)

XC2S15 Spartan-II FPGA (Xilinx)

XC2S150 Spartan-II FPGA (Xilinx)

XC2S150E Spartan-IIE FPGA (Xilinx)

XC2S200 Spartan-II FPGA (Xilinx)

XC2S200E Spartan-IIE FPGA (Xilinx)

XC2S30 Spartan-II FPGA (Xilinx)

XC2S300E Spartan-IIE FPGA (Xilinx)

TAGS

XC2S100 Spartan-II FPGA Xilinx

XC2S100 Distributor