XC5202 - Field Programmable Gate Arrays

This page provides the datasheet information for the XC5202, a member of the XC5200 Field Programmable Gate Arrays family.

Datasheet Summary

Features

Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Price competitive with Gate Arrays.
System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRing™ I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG bound.

Xilinx

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Datasheet Details

Part number	XC5202
Manufacturer	Xilinx
File Size	568.70 KB
Description	Field Programmable Gate Arrays
Datasheet	XC5202 Datasheet
Additional preview pages of the XC5202 datasheet.

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Full PDF Text Transcription

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Product Obsolete or Under Obsolescence 0 R XC5200 Series Field Programmable Gate Arrays November 5, 1998 (Version 5.2) 0 7* Product Specification Features • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Price competitive with Gate Arrays • System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRing™ I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.

Published: Dec 17, 2017 |