NJ88C50 Datasheet - Zarlink Semiconductor

NJ88C50 Dual Low Power Frequency Synthesiser

of each block and its function is given later in this datasheet. The synthesiser consists of the following blocks - 35MHz reference frequency input buffer - 35MHz programmable reference divider - 125MHz Auxiliary synthesiser input buffer - 125MHz Auxiliary synthesiser programmable divider - Auxiliar.

www.DataSheet4U.com NJ88C50 Dual Low Power Frequency Synthesiser DS3805 ISSUE 1.8 June 2002 The NJ88C50 is a low power integrated circuit, designed as the heart of a fast locking PLL subsystem in a mobile radio application. It is manufactured on Mitel Semiconductor 1.4 micron double polysilicon CMOS process, which ensures that low power and low noise performance is achieved. The device contains two synthesisers, one for the generation of VHF signals up to 125MHz and a second for UHF (when u.

NJ88C50 Features

* 30MHz main synthesiser 125MHz auxiliary synthesiser Programmable output current from phase detector - up to 10mA High input sensitivity Fractional-N interpolator Supports up to 4 modulus prescalers SSOP package DATA CKIN STROBE R

NJ88C50_ZarlinkSemiconductor.pdf