54F109
586.73kb
Dual j-k positive-edge-triggered flip-flop. These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs s
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ą
SDFS052A − D2932, MARCH 1987 − REVISED OCTOBER 1993
• Permits Multiplexing From N Lines .
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