74AC11109 Datasheet - Texas Instruments

74AC11109 Dual J-K Positive-edge-Triggered Flip-Flops

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time r.

ăą 54AC11109, 74AC11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCAS450 MARCH 1987 REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 Package Options.

74AC11109-etcTI.pdf