CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 JANUARY 2003 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT112 .
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F PACKAGE CD74ACT112 .
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M PACKAGE (T