CD74HC137 - High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer
Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes.
A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder.
Two Output Enable
CD74HC137 Features
* Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237
* l/O Port or Memory Selector
* Two Enable Inputs to Simplify Cascading
* Typical Propagation Delay of 13ns 15pF, TA = 25oC (CD74HC237) at VCC
