* low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go
CD74HC138-Q1 Datasheet (235.02 KB)
CD74HC138-Q1
235.02 KB
3- to 8-line inverting decoder/demultiplexer.
CD74HC138-Q1
HIGH-SPEED CMOS LOGIC
3- TO 8-LINE INVERTING DECODER/DEMULTIPLEXER
SCLS580A
* APRIL 2004
* REVISED APRIL 2008
D Qualifie.
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