CDC208 - Dual 1-Line To 4-Line Clock Drivers
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2).
The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or t
ąą D Low-Skew Propagation Delay Specifications for Clock-Driver Applications D TTL-Compatible Inputs and CMOS-Compatible Outputs D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (DW) CDC208 DUAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SCAS109F AP
