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CDC2509C 3.3-V Phase-Lock-Loop Clock Driver

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Description

CDC2509C 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS620A * DECEMBER 1998 * REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for .
The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

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Applications

* D Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs D Separate Output Enable for Each Output Bank D External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input D On-Chip Series Damping Resistors D No External RC Network Required D Operates at 3.

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