CDC2582 Datasheet - Texas Instruments

3.3-V Phase-Lock-Loop Clock Driver

D Low Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs D Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379B .

CDC2582 General Description

The CDC2582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifically designed to operate at speeds from 50 MHz to .

CDC2582 Datasheet (140.52 KB)