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CDC2582 3.3-V Phase-Lock-Loop Clock Driver

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Description

D Low Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D Distributes Differential LVPECL Clock Inputs to 1.
The CDC2582 is a high-performance, low-skew, low-jitter clock driver.

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Applications

* D Operates at 3.3-V VCC D Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs D Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Input (FBIN) Is Used to Synchronize the Outp

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