D Low Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs D Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379B
Datasheet Details
Part number:
CDC2582
Manufacturer:
File Size:
140.52 KB
Description:
3.3-v phase-lock-loop clock driver.