CDC2351 - 1-LINE TO 10-LINE CLOCK DRIVER
The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution.
The output-enable (OE) input disables the outputs to a high-impedance state.
Each output has an internal series damping resistor to improve signal integr
D Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D LVTTL-Compatible Inputs and Outputs D Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) D Distributes One Clock Input to Ten Outputs D Outputs Have Internal Series Damping Resistor to Reduce Transmission Line Effects D Distributed VCC and Ground Pins Reduce Switching Noise D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Diss
