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CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

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Description

CDC3RL02 SCHS371G * NOVEMBER 2009 * REVISED NOVEMBER 2022 CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer 1 .
The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as mobile phones, that require clock bufferin.

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Features

* Low Additive Noise:
* 149 dBc/Hz at 10-kHz Offset Phase Noise
* 0.37 ps (RMS) Output Jitter
* Limited Output Slew Rate for EMI Reduction (1- to 5-ns Rise/Fall Time for 10-pF to 50-pF Loads)
* Adaptive Output Stage Controls Reflection
* Regul

Applications

* Cellular Phones
* Global Positioning Systems (GPS)
* Wireless LAN
* FM Radio
* WiMAX
* W-BT VBATT LDO VLDO GND VCC EN CLK_OUT1 CLK_REQ1 MCLK_IN VCC EN CLK_OUT2 CLK_REQ2 Switch/ Decoder Copyright © 2017, Texas Instruments Incorporated Simpli

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