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CDC5801A Low Jitter Clock Multiplier/Divider

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Description

CDC5801A LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS813A * AUGUST 2005 * REVISED DECEMBER.
The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKO.

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Applications

* Video Graphics, Gaming Products, Datacom, Telecom D Accepts LVCMOS, LVTTL Inputs for REFCLK Terminal D Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper VDDREF Voltage Level (For Example, HSTL 1.5 if VDDREF = 1.6 V) D Supports Industrial Temperature Range of

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📌 All Tags

Low Jitter Clock Multiplier Divider Texas Instruments
Texas Instruments CDC5801A-like datasheet
CDC5806
CDC582
CDC586
CDC509
CDC516