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CDCP1803 1:3 LVPECL CLOCK BUFFER

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Description

www.ti.com CDCP1803 SCAS727F * NOVEMBER 2003 * REVISED DECEMBER 2013 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER Check for Sam.
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with.

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Features

* 1
* Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs
* Programmable Output Divider for Two LVPECL Outputs
* Low-Output Skew 15 ps (Typical)
* VCC Range 3 V
* 3.6 V
* Signaling Rate Up to 800-MHz LVPECL
* Differe

Applications

* the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference. RGE PACKAGE (TOP VIEW) S2 VDD0 Y0 Y0 VDD0 S1 EN VDDPECL IN IN VDDPECL VBB 24 23 22 21 20 19 1 18 2 17 3 VSS(1) 16 4 15 5 14 6 13 7 8 9 10 11 12

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