SN65LVDS96 - LVDS SERDES RECEIVER

Texas Instruments

SN65LVDS96 Datasheet Preview — Preview of SN65LVDS96 PDF

Datasheet Details

Part number	SN65LVDS96
Manufacturer	Texas Instruments ↗
File Size	479.82 KB
Description	LVDS SERDES RECEIVER
Datasheet	SN65LVDS96-etcTI.pdf

SN65LVDS96 Product details

Description

The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.

Features

3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput.
Suited for Point-to-Point Subsystem Communication With Very Low EMI.
3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out.
Operates From a Single 3.3-V Supply and 250 mW (Typ).
5-V Tolerant SHTDN Input.
Rising Clock Edge Triggered Outputs.
Bus Pins Tolerate 4-kV HBM ESD.
Packaged in Thin Shrink Sm.

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Published: Aug 6, 2024 |