SN65LVDS96 - LVDS SERDES RECEIVER
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.
These functions allow receipt of synchronous data from
SN65LVDS96 Features
* 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput
* Suited for Point-to-Point Subsystem Communication With Very Low EMI
* 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
* Operates Fr
