* gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low,
SN74HC166A-EP Datasheet (387.29 KB)
SN74HC166A-EP
387.29 KB
8-bit parallel-load shift register.
SN74HC166AĆEP 8ĆBIT PARALLELĆLOAD SHIFT REGISTER SCLS559 JANUARY 2004 D Controlled Baseline One Assembly/Test Site, One Fabricat.
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