* gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GND 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CLR serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-f
SN74HC166A-Q1 Datasheet (674.30 KB)
SN74HC166A-Q1
674.30 KB
8-bit parallel-load shift register.
SN74HC166AĆQ1 8ĆBIT PARALLELĆLOAD SHIFT REGISTER SCLS538A AUGUST 2003 REVISED APRIL 2008 D Qualified for Automotive Applications.
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