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SN74HC166A-Q1 8-BIT PARALLEL-LOAD SHIFT REGISTER

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Description

SN74HC166AĆQ1 8ĆBIT PARALLELĆLOAD SHIFT REGISTER SCLS538A * AUGUST 2003 * REVISED APRIL 2008 D Qualified for Automotive Applications.
ordering information This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input.

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Features

* gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GND 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CLR serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-f

Applications

* D Low Input Current of 1 µA Max D ESD Protection Exceeds 2000 V Per D Synchronous Load MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Wide Operating Voltage Range of 2 V to 6 V D Direct Overriding Clear D Parallel-to-Serial Conversion D Outputs Can Drive Up T

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