Datasheet4U Logo Datasheet4U.com

SN74LV11A-EP TRIPLE 3-INPUT POSITIVE-AND GATES

SN74LV11A-EP Description

SN74LV11AĆEP TRIPLE 3ĆINPUT POSITIVEĆAND GATE D Controlled Baseline * One Assembly/Test Site, One Fabrication Site D Extended Temperature Per.
ordering information This triple 3-input positive-AND gate is designed for 2-V to 5.

SN74LV11A-EP Applications

* using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING
* 40°C to 105°C TSSOP
* PW Tape and reel SN74LV11ATPWREP LV11AEP ‡ Packag

📥 Download Datasheet

Preview of SN74LV11A-EP PDF
datasheet Preview Page 2 datasheet Preview Page 3

📁 Related Datasheet

  • SN74LVC1G125 - high performance non-inverting buffer (UMW)
  • SN74LVC1G34 - Single buffer (UMW)
  • SN74L71 - AND-Gate R-S Master-Slave F-F (National Semiconductor)
  • SN74L74N - Dual D-Type Flip-Flop (ETC)
  • SN74LS00 - QUAD 2-INPUT NAND GATE (Motorola)
  • SN74LS02 - QUAD 2-INPUT NOR GATE (Motorola)
  • SN74LS04 - Hex Inverter (ON Semiconductor)
  • SN74LS04D - Hex Inverter (ON Semiconductor)

📌 All Tags

Texas Instruments SN74LV11A-EP-like datasheet