Datasheet4U.com

SN74LVC112A - Dual Negative-Edge-Triggered J-K Flip-Flop

Texas Instruments

📥 Download Datasheet

SN74LVC112A Datasheet Preview — Preview of SN74LVC112A PDF

datasheet Preview Page 2

datasheet Preview Page 3

Datasheet Details

Part number	SN74LVC112A
Manufacturer	Texas Instruments ↗
File Size	1.05 MB
Description	Dual Negative-Edge-Triggered J-K Flip-Flop
Datasheet	SN74LVC112A-etcTI.pdf

SN74LVC112A Product details

Description

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.

Features

1 Operates From 1.65 V to 3.6 V.
Inputs Accept Voltages to 5.5 V.
Max tpd of 4.8 ns at 3.3 V.
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C.
Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C.
Latch-Up Performance Exceeds 250 mA Per JESD 17.
ESD Protection Exceeds JESD 22.
3000-V Human-Body Model.
200-V Machine Model.
1500-V Charged-Device Model 2.

📁 SN74LVC112A Similar Datasheet

SN74LVC1G125 - high performance non-inverting buffer (UMW)
SN74LVC1G34 - Single buffer (UMW)
SN74L71 - AND-Gate R-S Master-Slave F-F (National Semiconductor)
SN74L74N - Dual D-Type Flip-Flop (ETC)
SN74LS00 - QUAD 2-INPUT NAND GATE (Motorola)
SN74LS02 - QUAD 2-INPUT NOR GATE (Motorola)
SN74LS04 - Hex Inverter (ON Semiconductor)
SN74LS04D - Hex Inverter (ON Semiconductor)

Other Datasheets by Texas Instruments

SN74LVC10A - TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74LVC125A - Quadruple Bus Buffer Gate
SN74LVC125A-EP - Quadruple Bus Buffer Gate
SN74LVC125A-Q1 - Automotive Quadruple Bus Buffer Gate
SN74LVC126A - Quadruple Bus Buffer
SN74LVC126A-Q1 - Automotive Quadruple Bus Buffer Gate

Published: Nov 14, 2020 |