SN74LVT125 Datasheet - Texas Instruments

SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS

D Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) D Supports Unregulated Battery Operation Down to 2.7 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine .

SN74LVT125 Features

* independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not rec

SN74LVT125 Datasheet (762.65 KB)