74AHC138 Datasheet (nexperia) - 3-to-8 line decoder/demultiplexer

74AHC138, 3-to-8 line decoder/demultiplexer

The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7A.

The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer.

It accepts three binary weighted address inputs (A0, A1

74AHC138 Features

* Balanced propagation delays

* All inputs have Schmitt-trigger action

* Demultiplexing capability

* Multiple input enable for easy expansion

* Ideal for memory chip select decoding

* Inputs accepts voltages higher than VCC

* For 74AHC138 only: