74AHC132 Datasheet - NXP

74AHC132 Quad 2-input NAND Schmitt trigger

The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of transforming slowl.

74AHC132 Features

* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

* Balanced propagation delays

* Inputs accepts voltages higher than VCC

* For AHC only: operates with CMOS input levels

* For AHCT onl

74AHC132_PhilipsSemiconductors.pdf