74AHC138 Datasheet - NXP

74AHC138 3-to-8 line decoder/demultiplexer

74AHC138; 74AHCT138 The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0, A1 and A2) and when enabled.

74AHC138 Features

* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

* Balanced propagation delays

* All inputs have Schmitt-trigger actions

* Multiple input enable for easy expansion

* Ideal for memory c

74AHC138_PhilipsSemiconductors.pdf