74AHC138D Datasheet - nexperia

3-to-8 line decoder/demultiplexer

74AHC138D Features

* Balanced propagation delays

* All inputs have Schmitt-trigger action

* Demultiplexing capability

* Multiple input enable for easy expansion

* Ideal for memory chip select decoding

* Inputs accepts voltages higher than VCC

* For 74AHC138 only:

74AHC138D General Description

The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1.

74AHC138D Datasheet (256.07 KB)