74AHC139 Datasheet (nexperia) - Dual 2-to-4 line decoder/demultiplexer

74AHC139, Dual 2-to-4 line decoder/demultiplexer

The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is speciﬁed in compliance with JEDEC standard No.

7-A.

The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer.

This device has two independent decoders,

74AHC139 Features

* I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Input levels: N For 74AHC139: CMOS level N For 74AHCT139: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C e