74AHC273PW, 74AHC273 Datasheet - nexperia

74AHC273PW Octal D-type flip-flop

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clo.

74AHC273PW Features

* Balanced propagation delays

* All inputs have Schmitt-trigger actions

* Inputs accept voltages higher than VCC

* Ideal buffer for MOS microcontroller or memory

* Common clock and master reset

* Input levels:

* For 74AHC273: CMOS level

74AHC273-nexperia.pdf