74AUP1G80 Datasheet (nexperia) - Low-power D-type flip-flop

74AUP1G80, Low-power D-type flip-flop

The 74AUP1G80 is a single positive-edge triggered D-type flip-flop.

Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output.

Schmitt-trigger action at all inputs makes the

74AUP1G80 Features

* Wide supply voltage range from 0.8 V to 3.6 V

* CMOS low power dissipation

* High noise immunity

* Complies with JEDEC standards:

* JESD8-12 (0.8 V to 1.3 V)

* JESD8-11 (0.9 V to 1.65 V)

* JESD8-7 (1.65 V to 1.95 V)

* JESD8-5 (2.3 V t