74HC107

Dual JK flip-flop

nexperia

74HC107 Features

* Wide supply voltage range from 2.0 V to 6.0 V

* CMOS low power dissipation

* High noise immunity

* Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

* Complies with JEDEC standards:

* JESD8C (2.7 V to 3.6 V)

* JESD7A (2.0 V to

74HC107 General Description

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the sta.

74HC107 Datasheet (262.00 KB)

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