HEF4520BT Datasheet PDF - nexperia Dual binary counter Specs

HEF4520BT - Dual binary counter

This page provides the datasheet information for the HEF4520BT, a member of the HEF4520B Dual binary counter family.

Datasheet Summary

Description

The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0 and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR).

Features

Tolerant of slow clock rise and fall times.
Fully static operation.
5 V, 10 V, and 15 V parametric ratings.
Wide supply voltage range from 3.0 V to 15.0 V.
CMOS low power dissipation.
High noise immunity.
Standardized symmetrical output characteristics.
Complies with JEDEC standard JESD 13-B.
ESD protection:.
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
CDM: ANSI/ESDA/JEDEC JS-002 class C3.

Datasheet Details

Part number	HEF4520BT
Manufacturer	nexperia
File Size	265.36 KB
Description	Dual binary counter
Datasheet	HEF4520BT Datasheet
Additional preview pages of the HEF4520BT datasheet.

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Full PDF Text Transcription

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HEF4520B Dual binary counter Rev. 9 — 19 August 2024 Product data sheet 1. General description The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0 and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2.

Published: Dec 2, 2024 |