A43L1616 Datasheet | AMIC Technology

Features Power supply - VDD: 3.3V VDDQ : 3.3V LVTTL patible with multiplexed address Two banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) Clock Frequency (max) : 167MHz @ CL=3 (-6) 143MHz @ CL=3 (-7) 1M X 16 Bit X 2 Banks Synchronous DRAM All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Industrial operating temperature range: -40ºC to +85ºC for -U series. Available in 54-pin TSOP(II) package Package is available to lead free (-F series) General Description The A43L1616 is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Configuration 54 TSOP (II) VDDQ VSSQ DQ15 DQ12 DQ14 DQ13 DQ11 DQ10 UDQM VDDQ VSSQ CKE VSS VSS DQ8 VSS VDD DQ9 NC CK A11 NC A9 A8 A7 A6 A5 A2 A4 A3 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A43L1616V 1 VDD 2 DQ0 3 VDDQ 4 DQ1 5 DQ2 6 VSSQ 7 DQ3 8 DQ4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VSSQ WE CAS RAS CS A10/AP A0 DQ5 DQ6 DQ7 LDQM VDDQ VDD BA NC A1 PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. Block Diagram LWE I/O Control Bank Select Data Input Register Row Buffer Refresh Counter Row Decoder Output Buffer 1M X 16 Sense AMP Address Register 1M X...