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LP62P16128C-T - 128K X 16 BIT LOW VOLTAGE CMOS SRAM

General Description

The LP62P16128C-T is a low operating current 2,097,152-bit static random access memory organized as 131,072 words by 16 bits and operates on low power voltage from 2.3V to 2.7V.

It is built using AMIC's high performance CMOS process.

Key Features

  • n Operating voltage: 2.3V to 2.7V n Access times: 120 ns (max. ) n Current: Very low power version: Operating: 20mA (max. ) Standby: 100µA (max. ) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min. ) n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm) packages 128K X 16 BIT LOW.

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Datasheet Details

Part number LP62P16128C-T
Manufacturer AMIC Technology
File Size 163.56 KB
Description 128K X 16 BIT LOW VOLTAGE CMOS SRAM
Datasheet download datasheet LP62P16128C-T Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LP62P16128C-T Series Preliminary Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 128K X 16 BIT LOW VOLTAGE CMOS SRAM History Initial issue Issue Date March 11, 2002 Remark Preliminary PRELIMINARY (March, 2002, Version 0.0) AMIC Technology, Inc. LP62P16128C-T Series Preliminary Features n Operating voltage: 2.3V to 2.7V n Access times: 120 ns (max.) n Current: Very low power version: Operating: 20mA (max.) Standby: 100µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.