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AT32A423 - 32-bit MCU+FPU

General Description

10 2 Functionality overview 13 2.1 ARM®Cortex®-M4 with FPU 13 2.2 Memory 13 2.2.1 Flash memory13 2.2.2 Memory protection unit (MPU) 13 2.2.3 Embedded SRAM13 2.2.4 External memory controller (XMC)14 2.3 Interrupts 14 2.3.1 Nested vectored interrupt controller (NVIC)

Key Features

  • AEC Q-100 certification.
  • Core: ARM® 32-bit Cortex®-M4 CPU with FPU.
  • 150 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division.
  • Floating point unit (FPU).
  • DSP instructions.
  • Memories.
  • 64 to 256 Kbytes of Flash memory.
  • 20 Kbytes of boot memory used as a Bootloader or as a general instruction/data memory (one-time-configurable).
  • sLib: configurable part of main Flash as a lib.

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Datasheet Details

Part number AT32A423
Manufacturer ARTERY
File Size 2.74 MB
Description 32-bit MCU+FPU
Datasheet download datasheet AT32A423 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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AT32A423 Series Datasheet ARM®-based 32-bit Cortex®-M4 MCU+FPU, 64 to 256 KB Flash, sLib, 15 timers, 1 ADC, 18 communication interfaces (2 CAN and 1 OTGFS) Features  AEC Q-100 certification  Core: ARM® 32-bit Cortex®-M4 CPU with FPU − 150 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division − Floating point unit (FPU) − DSP instructions  Memories − 64 to 256 Kbytes of Flash memory − 20 Kbytes of boot memory used as a Bootloader or as a general instruction/data memory (one-time-configurable) − sLib: configurable part of main Flash as a library area with code executable but secured, non-readable − Up to 48 Kbytes of SRAM − External memory controller (XMC) with 16bit data bus supporting multiplexed PSRAM and NOR memories  XMC as L