AT32L021 Datasheet | ARTERY

Features - Core: ARM® 32-bit Cortex® -M0+ CPU - 80 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication - Hardware divider - Memories - 16 to 64 KB of internal Flash memory - 4 Kbytes of boot memory as a Bootloader, or as a general instruction/data memory (one-time-configurable) - s Lib: configurable part of main Flash set as a library area with code executable but secured, non-readable - 9 Kbytes of SRAM (8 Kbytes with parity check) - Power control (PWC) - 1.71 to 3.6 V power supply - Power-on reset (POR), low voltage reset (LVR) and power voltage monitoring (PVM) - Low power modes: Sleep, Deepsleep and Standby modes; 5 WKUP pins for wakeup from Standby mode - 5 x 32-bit battery powered registers (BPR) - Clock and reset management (CRM) - 4 to 25 MHz crystal oscillator (HEXT) - Internal 48 MHz factory-trimmed HICK - 32 k Hz crystal (LEXT) - Low speed internal clock (LICK) - Analog - 1 x 12-bit 2 MSPS A/D converter, up to 15 external input channels; 12/10/8/6-bit configurable resolution; hardware oversampling up to equivalent 16-bit resolution - Internal reference voltage (VINTRV) - DMA - 1 x 5-channel DMA controller - Up to 39 fast GPIOs - Core dedicated single-cycle GPIO bus - All mappable on 16 external interrupts (EXINT) - Almost all 5 V-tolerant - Up to 10 timers (TMR) - 1 x 16-bit 7-channel advanced timer, including 3 pairs of plementary channels for PWM output, with dead-time generator and emergency brake - Up to 5 x 16-bit timers, each with 4 IC/OC /PWM or pulse counter and quadrature (incremental) encoder input - 1 x 16-bit basic timer - 2 x watchdog timers (general WDT and windowed WWDT) - Sys Tick timer: a 24-bit downcounter - ERTC: enhanced RTC, with alarm, subsecond accuracy, hardware calendar, and calibration - Up to 10 munication interfaces - 2 x I2C interfaces (SMBus/PMBus) supporting fast mode plus (1 MHz), with wakeup from Deepsleep mode - 2 x SPIs (36 MHz), both with multiplexed as half-duplex...