AT79C1010 Datasheet | Atmel

Features - - - - - - - - - - 4 10/100M Ethernet MII Ports Meet Fast Ethernet Requirements Provides Packets Switching Function Between 4 Ethernet Ports Crossbar Switching Engine Performs Switching at Wire Speed Full/Half Duplex Mode Interface Supported Flow Control for Full-duplex Supported MAC Address Table is Integrated in the Single-chip MAC Address Aging is Supported Input/Output Buffer Memory Embedded for Each Port MDIO Interface is Supported Available in a Variety of Packages Depending on Customer Requirements Description The AT79C1010 is an Ethernet switch controller that performs Layer 2 Switching according to IEEE 802 standards. It adopts the crossbar architecture to plete the function of packets switching between 4 MII ports. The mechanism of this switch is “learning & forwarding”, and the embedded MAC address table ensures the implementation of this function. It can attain wire speed when it's used as a fast Ethernet switch. 4-port Layer 2 Unmanaged Switched Ethernet Controller AT79C1010 Summary 3433AS- NETST- 2/04 Note: This is a summary document. A plete document is available under NDA. For more information, please contact your local Atmel sales office. Figure 1. AT79C1010 Block Diagram Core_Logic RX_CTR0 AP_REQ0 AP_ACK0 MAC_Bus0[31:0] AP_Cancel0 Data_Rate0[1:0] AP_END0 Duplex_Mode0 Port Data0[2:0] SYSCLK RESET MII RXD Interface RX0_SREQ RX0_CLK RXD0[3:0] RX0_ER RX0_DV COL0 RX0_SPACK RX0_SDACK Addressing SYSCLK AP_REQ[3:0] MAC_Bus0[31:0] MAC_Bus1[31:0] MAC_Bus2[31:0] MAC_Bus3[31:0] AP_ACK[3:0] AP_Cancel[3:0] AP_END[3:0] Port Data0[2:0] Port Data1[2:0] Port Data2[2:0] Port Data3[2:0] REG_CTR Mgmt_ITF SYSCLK MGMT_END MGMT_EN MDIO PRE_SUP MDC MEMT_RW MGMT_DATA[15:0] MGMT_REGAD[4:0] MGMT_PHYAD[4:0] Mgmt Interface to PHY chip REG_TAB FC_Mode0 FC_REQ0 FC_ACK0 RXD_Buf0 RX0_RP RX0_RE RX0_WP RX0_WE IRXD0[7:0] SYSCLK RX0_RP RX0_RE RX0_WP RX0_WE IRXD0[7:0] Data_CTR BUF_Switch RX_SREQ[3:0] RX_SPACK[3:0] RX_SDACK[3:0] REG_EN REG_RW REG_REGAD[3:0]...