AT89C51CC02 Datasheet | Atmel

Features - 80C51 Core Architecture - 256 Bytes of On-chip RAM - 256 Bytes of On-chip XRAM - 16K Bytes of On-chip Flash Memory - Data Retention: 10 Years at 85°C - Erase/Write Cycle: 100K - Boot Code Section with Independent Lock Bits - 2K Bytes of On-chip Flash for Bootloader - In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability - 2K Bytes of On-chip EEPROM - Erase/Write Cycle: 100K - 14-sources 4-level Interrupts - Three 16-bit Timers/Counters - Full Duplex UART patible 80C51 - Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz) - Three or Four Ports: 16 or 20 Digital I/O Lines - Two-channel 16-bit PCA - PWM (8-bit) - High-speed Output - Timer and Edge Capture - Double Data Pointer - 21-bit Watchdog Timer (7 Programmable bits) - A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs - Full CAN Controller - Fully pliant with CAN rev.# 2.0A and 2.0B - Optimized Structure for munication Management (Via SFR) - 4 Independent Message Objects -Each Message Object Programmable on Transmission or Reception -Individual Tag and Mask Filters up to 29-bit Identifier/Channel -8-byte Cyclic Data Register (FIFO)/Message Object -16-bit Status and Control Register/Message Object -16-bit Time-Stamping Register/Message Object -CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object -Access to Message Object Control and Data Registers Via SFR -Programmable Reception Buffer Length up to 4 Message Objects -Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature ) -Priority Management for Transmission -Message Object Overrun Interrupt - Supports -Time Triggered munication -Autobaud and Listening Mode -Programmable Automatic Reply Mode - 1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode - Readable Error Counters - Programmable Link to On-chip Timer for Time Stamping and Network Synchronization - Independent Baud Rate Prescaler -...