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M1A3P400 - ProASIC3 Flash Family FPGAs

Download the M1A3P400 datasheet PDF. This datasheet also covers the M1A3P1000 variant, as both devices belong to the same proasic3 flash family fpgas family and are provided as variant models within a single manufacturer datasheet.

General Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and

Key Features

  • High Capacity.
  • 15 k to 1 M System Gates.
  • Up to 144 kbits of True Dual-Port SRAM.
  • Up to 300 User I/Os ® Reprogrammable Flash Technology.
  • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off High Performance.
  • 350 MHz System Performance.
  • 3.3 V, 66 MHz 64-Bit PCI† Clock Conditioning Circuit (CCC) and PLL†.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M1A3P1000_ActelCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M1A3P400
Manufacturer Actel Corporation
File Size 5.99 MB
Description ProASIC3 Flash Family FPGAs
Datasheet download datasheet M1A3P400 Datasheet

Full PDF Text Transcription for M1A3P400 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for M1A3P400. For precise diagrams, and layout, please refer to the original PDF.

v1.0 www.DataSheet4U.com ProASIC3 Flash Family FPGAs with Optional Soft ARM® Support Features and Benefits High Capacity • 15 k to 1 M System Gates • Up to 144 kbits of T...

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nefits High Capacity • 15 k to 1 M System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os ® Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off High Performance • 350 MHz System Performance • 3.3 V, 66 MHz 64-Bit PCI† Clock Conditioning Circuit (CCC) and PLL† • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI /